We are in a world today where our consumer devices support a billion transistors, a multitude of packages and components and multiple functionalities. As we continue to make progress in the electronics industry, new technologies will emerge that provide us with smaller and better devices, increase in integrated components, smaller and more advanced packages and even more functionality. With such advances, the interface between the devices, circuits, packages and systems will continue to diminish where it will become difficult to separate these regions for managing signal, power and thermal integrity ? three aspects of the problem that are pristine for ensuring system performance. In this talk, advanced technologies leading to system miniaturization will be discussed in the context of signal, power and thermal management.

We are in a world today where our consumer devices support a billion transistors, a multitude of packages and components and multiple functionalities. As we continue to make progress in the electronics industry, new technologies will emerge that provide us with smaller and better devices, increase in integrated components, smaller and more advanced packages and even more functionality. With such advances, the interface between the devices, circuits, packages and systems will continue to diminish where it will become difficult to separate these regions for managing signal, power and thermal integrity ? three aspects of the problem that are pristine for ensuring system performance. In this talk, advanced technologies leading to system miniaturization will be discussed in the context of signal, power and thermal management.

The leading-edge power & signal integrity technologies of the Samsung System LSI are introduced with real best practice cases covering from silicon to platform. This demonstrates how to achieve cost-effective power/signal integrity designs and solutions for the high-performance Samsung mobile systems.

Dr. Ryu is a Senior Engineering Department manager at Samsung Electronics Co., Ltd. with responsibility for power/signal integrity (PSI) and electrical validation enabling for all AP/SOC and LSI silicon/platforms. From 2001 to 2011 he was a senior Engineering manager at Intel where he managed the SPIE team, which is responsible for pre-/post-silicon PSI analysis for future memory technology development and SOC Hard IP customers/platforms. Since 2008 he holds an IEEE Senior Member status and the co-author of a book titled "Power Integrity for I/O Interfaces: With Signal Integrity/Power Integrity Co-Design (Prentice Hall, April 2010)". He has authored/co-authored more than 90 technical publications in premier journals, international conferences. He serves as a technical program committee member for DesignCon. He was a best paper award recipient in recognition of my technical contributions to DesignCon2006 and DesignCon2008. He holds a Ph.D. in EE from KAIST.

The semiconductor industry has advanced as Moore's law predicted in last few decade. With the introduction of 3D IC, it has extended the Moore's law into another dimension. These 3D IC's are capable of enhancing overall chip performance and achieving high density heterogeneous system integration by utilizing through-silicon-vias (TSV), multiple die can be 3D stacked and/or stitching through Interposer into 3DIC platform.
  The 3DIC vast interconnecting capabilities and ultra-short die to die distance can be fully explored for high bandwidth, low power applications. With the 3DIC memory family become standard last year, this also made a full computer system within 3DIC.
  Here we shall introduce one of test vehicles using TSMC CoWoS(tm) platform and using one of the JEDEC standard WideIO DRAM. We shall use it as example to explore 3DIC system advantages, design for test challenges and proposed solutions. Also we shall share a brief lesson learned from this Test Vehicle as well as some suggestions for future considerations.

William (Bill) has worked in memory controller/system design area for more than 20 years. Experience background includes logic design, team leader for memory controller, memory-subsystem architect, lead system design engineer in multi-national companies, such as International Business Machine and LSI Corp.
  Currently he is Senior Manager, Test Chip Design Verification Division, TSMC Corp. at Hsinchu, Taiwan. He also serves as Vice Chairman of JEDEC JC42.3B DRAM Features and Functions Letter Committee. Bill has held both PHD and Master degree from Clarkson University, NY, U.S.A and BSEE degree from Taipei Institute of Technology, Taipei, Taiwan. Personal hobbies include reading, photography, fishing and audio amplify equipment.

The movement toward Smart Society is accelerating globally aiming efficient use of energy resources. To build an energy-saving product, it is necessary first of all to use low-power semiconductor devices, especially low-power microcontrollers as Smart Society brain. This presentation will introduce several applications of low-power microcontrollers for Smart Society and will mention EMC issues and solutions for the applications.

Dr. Shimizu received B.S., M.S., and Ph.D. degrees of Information Science from the University of Tokyo, Japan.
  Since 1986, he has been involved in microprocessor, microcontroller and SoC design R&D, working in Mitsubishi Electric, Renesas Technology, and Renesas Electronics.
  He has lead various projects developing embedded microprocessor products, such as RISC microprocessors with embedded DRAM, microcontrollers with embedded Flash, and multi-core SoCs. His R&D domain covers LSI architecture and design, as well as embedded application system design.
  He is a steering committee member of the Asian Solid-State Circuits Conference (A-SSCC), and an executive committee director of the Embedded Technology Conference in Japan. He is also a professor of Kanazawa Univ. and a professor of Future Univ. Hakodate, and he has been supporting collaborative activities between industry and academia.